A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo

A methodology and a case-study for Network-on-Chip based MP-SoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability of next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this work a complete design methodology is proposed, tackling at once the aspects of hardware architecture, programming model and design automation. The proposed design flow has been used in the implementation of a multiprocessor Network-on-Chip based system, the NoCRay graphic accelerator. The system uses 8 Tensilica LX processors and has been physically implemented on a Xilinx Virtex-4 LX-160 FPGA reporting a 17.3M equivalent gate-count. Performance are compared with a commercial general purpose processor and show good results considering the low frequency of the prototype

A methodology and a case-study for Network-on-Chipbased MP-SoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability of next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this work a complete design methodology is proposed, tackling at once the aspects of hardware architecture, programming model and design automation. The proposed design flow has been used in the implementation of a multiprocessor Network-on-Chip based system, the NoCRay graphic accelerator. The system uses 8 Tensilica LX processors and has been physically implemented on a Xilinx Virtex-4 LX-160 FPGA reporting a 17.3M equivalent gate-count. Performance are compared with a commercial general purpose processor and show good results considering the low frequency of the prototype

Multiparametric Implantable Cardioverter-Defibrillator Algorithm for Heart Failure Risk Stratification and Management: An Analysis in Clinical Practice

BACKGROUND: The HeartLogic algorithm combines multiple implantable cardioverter-defibrillator sensors to identify patients at risk of heart failure (HF) events. We sought to evaluate the risk stratification ability of this algorithm in clinical practice. We also analyzed the alert management strategies adopted in the study group and their association with the occurrence of HF events.METHODS: The HeartLogic feature was activated in 366 implantable cardioverter-defibrillator and cardiac resynchronization therapy implantable cardioverter-defibrillator patients at 22 centers. The median follow-up was 11 months [25th-75th percentile: 6-16]. The HeartLogic algorithm calculates a daily HF index and identifies periods IN alert state on the basis of a configurable threshold.RESULTS: The HeartLogic index crossed the threshold value 273 times (0.76 alerts/patient-year) in 150 patients. The time IN alert state was 11% of the total observation period. Patients experienced 36 HF hospitalizations, and 8 patients died of HF during the observation period. Thirty-five events were associated with the IN alert state (0.92 events/patient-year versus 0.03 events/patient-year in the OUT of alert state). The hazard ratio in the IN/OUT of alert state comparison was (hazard ratio, 24.53 [95% CI, 8.55-70.38], P<0.001), after adjustment for baseline clinical confounders. Alerts followed by clinical actions were associated with less HF events (hazard ratio, 0.37 [95% CI, 0.14-0.99], P=0.047). No differences in event rates were observed between in-office and remote alert management.CONCLUSIONS: This multiparametric algorithm identifies patients during periods of significantly increased risk of HF events. The rate of HF events seemed lower when clinical actions were undertaken in response to alerts. Extra in-office visits did not seem to be required to effectively manage HeartLogic alerts. Registration: URL: ; Unique identifier: NCT02275637